1. Field of the Invention
The present invention relates to an improved test structure and method for determining the electromigration characteristics of integrated circuits.
2. Description of the Prior Art
The high reliability of integrated circuits is a very significant factor in their production and use. Attempts are made to ensure high reliability in all stages of the production process. Where feasible, tests are performed at intermediate stages of production so that corrective action can be taken if necessary. The importance of this procedure can be understood when it is realized that modern IC production requires hundreds of steps in very carefully controlled environmental conditions. The completion of all the steps for a given wafer typically requires several weeks, or even months, before the final IC wafer is available for electrical testing of its circuits. Therefore, a large inventory of very valuable product is undergoing processing at any given time. If a problem develops at a process step, it may, under worst-case conditions, be several weeks before it is discovered, thereby resulting in a significant economic loss of wafers in process.
One area of traditional concern is the electromigration characteristics of metal (e.g., aluminum, aluminum alloys, and/or refractory metal) conductors in the integrated circuit. Because of the very small linewidths required for present-day IC's, the current density in these conductors, including runners and contacts, is very high, often exceeding 1.times.10.sup.5 amps/cm.sup.2 in normal device operation. Therefore, if the metal is inadvertently thinner (or narrower) in some portions of the runner than in others, the current density will be even higher than the intended value at those locations. Since the failure rate due to electromigration problems increases rapidly as the current density increases, such unintended thinning of the runners may lead to unacceptable reliability of the IC. Still other factors may affect the electromigration characteristics, such as the presence of impurities or precipitates in the metal that forms the runners, the grain size of the metal, and various other geometry limiting effects.
The traditional means for determining the electromigration characteristics, and hence reliability, of the runners is to pass a current through a test structure on an IC wafer, and determine the time it takes for the test structure to fail. The failure may occur, for example, by the test conductor becoming non-conductive, or by one test conductor shorting out to another test conductor. A traditional test structure adopted by the National Bureau of Standards is shown in FIG. 4. A long, thin metal test conductor (400) is connected to broader metal conductors (401, 402) at either end, which connect to bondpads (403, 404) for supplying current from an external power supply. The length L of the test conductor is 800 micrometers, and the width of the broader metal conductors (W.sub.3) is twice that of the test conductor (W.sub.4). Voltage monitor test points are provided by conductors 405, 406, spaced L.sub.t =2.times.W.sub.3 from the ends of regions 401, 402, and connected to bondpads (407, 408). It is also known in the art to include side conductors (not shown) to determine by means of a short-circuit test whether metal migration occurs transversely to the test conductor.
The current density in the long-term test is typically about 1 to 3.times.10.sup.6 amps/cm.sup.2. In addition, the long-term test provides for the wafer to be heated to approximately 200 to 300 C. in order to accelerate the test as much as possible. However, even under these conditions the traditional long-term test requires typically a week or more of operation without a failure to prove that the electromigration characteristics are satisfactory.
A more recent electromigration test technique is termed "SWEAT" (Standard Wafer-level Electromigration Acceleration Test), which provides for passing a much larger current than used for the "long-term" test through a test structure that is optimized for the accelerated test. The large current provides for joule heating of the test conductor only, which avoids the necessity for heating the entire wafer. The time required for the SWEAT test is typically only about 30 seconds at a current density of about 1 to 2.times.10.sup.7 amps/cm.sup.2 for an aluminum runner. Therefore, SWEAT could potentially be used for monitoring wafer lots in real time, in the sense that the information gained is sufficiently timely that the process parameters can be changed before the next lot arrives at a given process stage. If desired, testing can even be accomplished on each wafer, with appropriate process changes being accomplished before the next wafer. The SWEAT technique is described in "Wafer Level Electromigration Tests for Production Monitoring", B. J. Root et al, in the Proceedings of the International Reliability Physics Symposium, pp. 100-107 (1985 ).
The test structure used for the SWEAT test is shown in FIG. 3. The current is conducted from bondpads 301, 302 into the test structure through relatively wide end conductors 303 and 310. A plurality of relatively wide interior regions (304 . . . 309) alternate with relatively narrow regions (311 . . . 316). The width of the narrow regions is typically the same as the narrowest linewidth of the metal runners of the integrated circuits on the same wafer as the test structure. The alternation of the wide regions with narrow regions provides for abrupt thermal stress gradients that are thought necessary for the accelerated test. However, the SWEAT test has not been widely adopted in the semiconductor industry. This appears to be due to a lack of correlation between the results produced by SWEAT and the results produced by the more traditional long-term tests. Therefore, there is a need for an accelerated test technique that more accurately simulates the traditional long-term test, and hence give greater confidence as to its ability to accurately predict electromigration characteristics in actual device operation.